View LTC4266_4607110.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc4290/ltc4271 1 429071f n poe pse switches/routers n poe pse midspans applications features description 8-port poe/poe + pse controller the ltc ? 4290/ltc4271 chipset is an 8-port power sourc - ing equipment (pse) controller designed for use in ieee 802.3at type 1 and type 2 (high power) compliant power over ethernet (poe) systems. transformer-isolated com - munication protocol replaces expensive opto-couplers and complex isolated 3.3v supply resulting in significant bom cost savings. the ltc4290/ltc4271 chipset delivers lowest-in-industry heat dissipation by utilizing low-r ds(on) external mosfets and 0.25 sense resistors. advanced power management features include per-port 12- bit current monitoring adcs, dac-programmable current limit, and versatile fast shut-down of preselected ports. advanced power management host software is available under a no-cost license. pd discovery uses a proprietary dual-mode 4-point detection mechanism ensuring excel - lent immunity from false pd detection. midspan pses are supported with 2-event classification and a 2 second backoff timer. the ltc4290/ltc4271 includes an i 2 c serial interface operable up to 1mhz. n eight independent pse channels n compliant with ieee 802.3at type 1 and 2 n chipset provides electrical isolation reduced bom cost eliminates up to 6 high speed opto-couplers eliminates isolated 3.3v power supply n low power dissipation 0.25 sense resistance per channel n very high reliability 4-point pd detection 2-point forced voltage 2-point forced current n v ee and v port monitoring n 1 second rolling i port averaging n supports 2-pair and 4-pair output power n 1mhz i 2 c compatible serial control interface n available in a 40-lead 6mm 6mm (ltc4290) and 24-lead 4mm 4mm (ltc4271) qfn package l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and ltpoe ++ is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. typical application ?? 3.3v 3.3v 0.1f ?54v 100 100 100 100 ?? 3.3v 1f 1f 0.1f ?54v 100 100 100 100 gp0 gp1 mid reset msd int auto scl ad0 ad1 ad2 ad3 ad6 dgnd cap1 cap2 dnd dpd cnd cpd dna sense1 gate1 out1 ltc4290 dpa cna cpa xio0 xio1 0.22f 100v 0.22f 100v s1b s1b ?54v ?54v 429071 ta01a ?54v s1b s1b portn port1 sdain sdaout ltc4271 no isolation required on i 2 c interface v dd33 2nf 2kv v ee sensen gaten outn agnd vssk 0.25 0.25 ?54v >47f system bulk cap +
ltc4290/ltc4271 2 429071f absolute maximum ratings ltc4290 supply voltages agnd C v ee ........................................... C0.3v to 80v vssk (note 7) ..................... v ee C 0.3v to v ee + 0.3v digital pins xion ................................. v ee C 0.3v to cap2 + 0.3v analog pins sensen, gaten, outn ........ v ee C 0.3v to v ee + 80v cap2 (note 13) ....................... v ee C0.3v to v ee + 5v cpa, cna, dpa, dna .............. v ee C 0.3v to v ee + 0.3 operating ambient temperature range ltc4290i ............................................. C40c to 85c junction temperature (note 2) ............................ 125c storage temperature range .................. C65c to 150c (notes 1, 4) ltc4271 supply voltages v dd C dgnd ......................................... C0.3v to 3.6v digital pins scl, sdain, sdaout, int , reset , msd , adn, auto, mid, gpn ........................ dgnd C 0.3v to v dd + 0.3v analog pins cap1 (note 13) ........................... C0.3v to dgnd + 2v cpd, cnd, dpd, dnd ...... dgnd C 0.3v to v dd + 0.3v operating ambient temperature range ltc4271i .............................................. C40c to 85c junction temperature (note 2) ............................ 125c storage temperature range .................. C65c to 150c (note 1)
ltc4290/ltc4271 3 429071f pin configuration order information lead free finish tape and reel part marking package description max pwr temperature range ltc4271iuf#pbf ltc4271iuf#trpbf 4271 24-lead (4mm 4mm) plastic qfn C40c to 85c ltc4290biuj#pbf ltc4290biuj#trpbf ltc4290buj 40-lead (6mm 6mm) plastic qfn 25.5w C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc4290 ltc4271 12 11 13 14 15 top view 41 vssk uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 20 39 40 38 37 36 35 34 33 32 31 23 24 25 26 27 28 29 30 8 7 6 5 4 3 2 1v ee gate1 out1 gate2 out2 cap2 gate3 out3 gate4 out4 v ee gate8 out8 gate7 out7 agnd gate6 out6 gate5 out5 v ee cpa cna dpa dna nc nc v ee nc nc xio0 sense1 sense2 sense3 sense4 sense5 sense6 sense7 sense8 xio1 22 21 9 10 t jmax = 125c, jc = 2c/w exposed pad (pin 41) is vssk, must be soldered to pcb 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 ad0 ad1 ad2 ad3 ad6 mid scl sdain sdaout int reset dnc msd gp0 gp1 auto v dd33 cap1 nc cpd cnd dpd dnd v dd33 25 dgnd t jmax = 125c, jc = 4c/w exposed pad (pin 25) is dgnd, must be soldered to pcb
ltc4290/ltc4271 4 429071f electrical characteristics symbol parameter conditions min typ max units v ee main poe supply voltage agnd C v ee for ieee type 1 compliant output for ieee type 2 compliant output l l 45 51 57 57 v v undervoltage lock-out agnd C v ee l 20 25 30 v v dd v dd supply voltage v dd C dgnd l 3.0 3.3 3.6 v undervoltage lock-out v dd C dgnd 2.7 v v cap1 internal regulator supply voltage v cap1 C dgnd 1.84 v v cap2 internal regulator supply voltage v cap2 C v ee 4.3 v i ee v ee supply current (agnd C v ee ) = 55v l 9 15 ma r ee v ee supply resistance v ee < 15v l 12 k i dd v dd supply current (v dd C dgnd) = 3.3v l 10 15 ma detection detection current C forced current first point, agnd C v outn = 9v second point, agnd C v outn = 3.5v l l 220 143 240 160 260 180 a a detection voltage C forced voltage agnd C v outn , 5a i outn 500a first point second point l l 7 3 8 4 9 5 v v detection current compliance agnd C v outn = 0v l 0.8 0.9 ma v oc detection voltage compliance agnd C v outn , open port l 10.4 12 v detection voltage slew rate agnd C v outn , c port = 0.15f l 0.01 v/s min. valid signature resistance l 15.5 17 18.5 k max. valid signature resistance l 27.5 29.7 32 k classification v class classification voltage agnd C v outn , 0ma i outn 50ma l 16.0 20.5 v classification current compliance v outn = agnd l 53 61 67 ma classification threshold current class 0-1 class 1-2 class 2-3 class 3-4 class 4-overcurrent l l l l l 5.5 13.5 21.5 31.5 45.2 6.5 14.5 23 33 48 7.5 15.5 24.5 34.9 50.8 ma ma ma ma ma v mark classification mark state voltage agnd C v outn , 0.1ma i class 5ma l 7.5 9 10 v mark state current compliance v outn = agnd l 53 61 67 ma gate driver gate pin pull-down current port off, v gaten = v ee + 5v port off, v gaten = v ee + 1v l l 0.4 0.08 0.12 ma ma gate pin fast pull-down current v gaten = v ee + 5v 30 ma gate pin on voltage v gaten C v ee , i gaten = 1a l 8 12 14 v output voltage sense v pg power good threshold voltage v outn C v ee l 2 2.4 2.8 v out pin pull-up resistance to agnd 0v (agnd C v out ) 5v l 300 500 700 k the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v and v dd C dgnd = 3.3v unless otherwise noted. (notes 3 & 4)
ltc4290/ltc4271 5 429071f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v and v dd C dgnd = 3.3v unless otherwise noted. (notes 3 & 4) symbol parameter conditions min typ max units v cut overcurrent sense voltage v sensen C v ee , hpen = 0fh, cutn = d4h hpen = 0fh, cutn = e2h (note 12) l l 89 152 94 159 99 168 mv mv overcurrent sense in auto pin mode class 0, class 3 class 1 class 2 class 4 l l l l 89 26 49 152 94 28 52 159 99 30 55 168 mv mv mv mv v lim active current limit in 802.3af compliant mode v sensen C v ee , hpen = 0fh, limn = 80h, (agnd C v ee ) = 55v v ee < v out < agnd C 29v agnd C v out = 0v (note 12) l l 102 25 106 112 50 mv mv active current limit in high power mode hpen = 0fh, limn = c0h, (agnd C v ee ) = 55v v out C v ee = 0 C 10v v ee + 23v < v out < agnd C 29v agnd C v out = 0v (note 12) l l l 204 102 25 212 106 225 115 50 mv mv mv active current limit in auto pin mode v ee < v out < agnd C 10v, (agnd C v ee ) = 55v class 0 to class 3 class 4 l l 102 204 106 212 112 225 mv mv v min dc disconnect sense voltage v sense C v ee , rdis bit = 0 v sense C v ee , rdis bit = 1 (note 12) l l 2.6 1.3 3.8 1.9 4.9 2.45 mv mv v sc short-circuit sense v sensen C v ee C v lim (note 12) rdis bit = 0 rdis bit = 1 l l 125 70 200 100 255 125 mv mv port current readback resolution no missing codes, reported as 14 bits 12 bits lsb weight v sensen C v ee 30.518 v/lsb conversion period 25.1 ms/ convert port voltage readback resolution no missing codes, reported as 14 bits 12 bits lsb weight v sensen C v ee 5.8350 mv/lsb digital interface v ild digital input low voltage adn, reset, msd, gpn, auto, mid (note 6) l 0.8 v i 2 c input low voltage scl, sdain (note 6) l 1.0 v v ihd digital input high voltage (note 6) l 2.2 v digital output voltage low i sdaout = 3ma, i int = 3ma i sdaout = 5ma, i int = 5ma l l 0.4 0.7 v v internal pull up to v dd adn, reset, msd, gpn 50 k internal pull down to dgnd auto, mid 50 k
ltc4290/ltc4271 6 429071f symbol parameter conditions min typ max units xio v olx xio digital output low v xion C v ee , i xion = 5ma l 0.7 v v ohx xio digital output high v xion C v ee , i xion = 100a l 3.5 v xio digital input low voltage v xion C v ee l 0.8 v xio digital input high voltage v xion C v ee l 3.4 v internal pull up to cap2 xio0, xio1 50 k pse timing characteristics t det detection time beginning to end of detection (note 7) 220 ms t cle class event duration (note 7) 12 ms t cleon class event turn on duration c port = 0.6f (note 7) l 0.1 ms t me mark event duration (note 7, note 11) 8.6 ms t mel last mark event duration (note 7, note 11) l 16 22 ms t pon power on delay in auto pin mode from end of valid detect to application of power to port (note 7) l 60 ms turn-on rise time (agnd C v out ): 10% to 90% of (agnd - v ee ) c port = 0.15f (note 7) l 15 24 s turn-on ramp rate c port = 0.15f (note 7) l 10 v/s t tocl turn-on class transition c port = 0.15f (note 7) l 0.1 ms t ed fault delay from i cut or i lim fault to next detect (note 7) l 1.0 1.1 s midspan mode detection backoff r port = 15.5k (note 7) l 2.3 2.5 2.7 s power removal detection delay from power removal after t dis to next detect (note 7) l 1.0 1.3 2.5 s t start maximum current limit duration during port start-up (note 7) l 52 59 66 ms t cut maximum overcurrent duration after port start- up (note 7) l 52 59 66 ms maximum overcurrent duty cycle (note 7) l 5.8 6.3 6.7 % t lim maximum current limit duration after port start- up C t lim enabled t lim = 1 (note 7, note 12) l 10 12 14 ms maximum current limit duration after port start- up C t lim as t cut t lim = 0 (note 7, note 12) l 52 59 66 ms t mps maintain power signature (mps) pulse width sensitivity current pulse width to reset disconnect timer (note 7, note 8) l 1.6 3.6 ms t dis maintain power signature (mps) dropout time (note 7, note 5) l 320 350 380 ms t msd masked shut down delay (note 7) 6.5 s i 2 c watchdog timer duration (note 7) l 1.5 2 3 s minimum pulse width for masked shut down (note 7) l 3 s minimum pulse width for reset (note 7) l 4.5 s electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v and v dd C dgnd = 3.3v unless otherwise noted. (notes 3 & 4)
ltc4290/ltc4271 7 429071f symbol parameter conditions min typ max units i 2 c timing f sclk clock frequency (note 7) l 1 mhz t 1 bus free time figure 5 (notes 7, 9) l 480 ns t 2 start hold time figure 5 (notes 7, 9) l 240 ns t 3 scl low time figure 5 (notes 7, 9) l 480 ns t 4 scl high time figure 5 (notes 7, 9) l 240 ns t 5 sdain data hold time figure 5 (notes 7, 9) l 60 ns t 5 data clock to sdaout valid figure 5 (notes 7, 9) l 130 ns t 6 data set-up time figure 5 (notes 7, 9) l 80 ns t 7 start set-up time figure 5 (notes 7, 9) l 240 ns t 8 stop set-up time figure 5 (notes 7, 9) l 240 ns t r scl, sdain rise time figure 5 (notes 7, 9) l 120 ns t f scl, sdain fall time figure 5 (notes 7, 9) l 60 ns fault present to int pin low (notes 7, 9, 10) l 150 ns stop condition to int pin low (notes 7, 9, 10) l 1.5 s ara to int pin high time (notes 7, 9) l 1.5 s scl fall to ack low (notes 7, 9) l 130 ns electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. agnd C v ee = 54v and v dd C dgnd = 3.3v unless otherwise noted. (notes 3 & 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. with the exception of (v dd C dgnd), exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 140oc when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 3: all currents into device pins are positive; all currents out of device pins are negative. note 4: the ltc4290 operates with a negative supply voltage (with respect to agnd). to avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. note 5: t dis is the same as t mpdo defined by ieee 802.3 note 6: the ltc4271 digital interface operates with respect to dgnd. all logic levels are measured with respect to dgnd. note 7: guaranteed by design, not subject to test. note 8: the ieee 802.3 specification allows a pd to present its maintain power signature (mps) on an intermittent basis without being disconnected. in order to stay powered, the pd must present the mps for t mps within any t mpdo time window. note 9: values measured at v ild and v ihd note 10: if a fault condition occurs during an i 2 c transaction, the int pin will not be pulled down until a stop condition is present on the i 2 c bus. note 11: load characteristics of the ltc4290 during mark: 7v < (agnd C v outn ) < 10v or i out < 50a. note 12: see the ltc4271 software programming documentation for information on serial bus usage and device configuration and status registers. note 13: do not source or sink current from cap1 and cap2.
ltc4290/ltc4271 8 429071f classification transient response to 40ma load step typical performance characteristics powering up into a 180f load classification current compliance v dd supply current vs voltage v ee supply current vs voltage 802.3af power on sequence in auto pin mode 802.3at power on sequence in auto pin mode power on sequence with 10v pp 60hz noise forced current detection vee = ?55v class 3 pd vee 50ms/div ?60 port voltage (v) ?10 ?20 ?30 ?40 ?50 0 429071 g01 forced voltage detection 802.3af classification power on agnd forced current detection vee = ?55v class 4 pd vee 50ms/div ?60 port voltage (v) ?10 ?20 ?30 ?40 ?50 0 429071 g02 forced voltage detection 802.3at classification power on agnd agnd 50ms/div ?25 port voltage (v) 0 ?5 ?10 ?15 ?20 5 429071 g03 forced voltage detection 802.3af classification power on port off forced current detection normal detect detect with 60hz noise 5ms/div 429071 g04 fet on foldback vee = ?54v agnd vee vee 0ma port voltage 20v/div port current 200ma/div gate voltage 10v/div 425ma current limit load fully charged 50s/div 40ma 0ma 429071 g05 ?20v port voltage 1v/div port current 20ma/div v dd = 3.3v v ee = ?54v classification current (ma) 429071 g06 0 2010 30 40 50 60 70 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 classification voltage (v) v dd supply voltage (v) 429071 g07 2.7 2.92.8 3.0 3.1 3.2 3.3 3.4 3.63.5 15.0 12.0 9.0 6.0 3.0 0.0 i dd supply current (ma) ?40 25c 85c v ee supply voltage (v) 429071 g08 ?60 ?50 ?40 ?30 ?20 9.0 8.5 8.0 7.0 7.5 6.5 6.0 i ee supply current (ma) ?40 25c 85c
ltc4290/ltc4271 9 429071f 802.3at i lim threshold vs temperature typical performance characteristics dc disconnect threshold vs temperature 802.3at current limit foldback int and sdaout pull down voltage vs load current mosfet gate drive with fast pull down 802.3at i cut threshold vs temperature temperature (c) ?40 204 v lim (mv) i lim (ma) 216 212 208 220 816 864 848 832 880 40 60 80 100 120 ?20 0 429071 g09 20 port 1 reg 48h = c0h r sense = 0.25 temperature (c) ?40 152 v cut (mv) i cut (ma) 162 164 160 158 156 154 166 608 648 640 632 624 616 664 656 40 60 80 100 120 ?20 0 429071 g10 20 port 1 reg 47h = e2h r sense = 0.25 temperature (c) ?40 1.25 v min (mv) i min (ma) 2.00 2.25 1.75 1.50 2.50 5 8 7 6 10 9 40 60 80 100 120 ?20 0 429071 g11 20 port 1 reg 47h = e2h r sense = 0.25 v outn (v) ?54 0 i lim (ma) v lim (mv) 600 500 800 700 400 300 200 100 900 0 125 100 75 50 25 225 200 175 150 ?36 ?27 ?18 ?9 0 ?45 429071 g12 port 1 reg 48h = c0h r sense = 0.25 load current (ma) 429071 g13 0 2010 30 40 50 60 3.0 2.5 2.0 1.5 1.0 0.5 0.0 pulldown voltage (v) 100s/div gnd 0ma 429071 g14 v ee v ee port current 500ma/div gate voltage 10v/div port voltage 20v/div current limit 50 fault removed 50 fault applied v dd = 3.3v v ee = ?54v fast pull down
ltc4290/ltc4271 10 429071f test timing diagrams figure 1. detect, class and turn-on timing in auto pin or semi-auto modes figure 2. current limit timing figure 3. dc disconnect timing v portn int v oc v ee t det t me t mel v mark v class 15.5v 20.5v t cle t cle t cleon pd connected 0v 429071 f01 forced-current classification t pon forced- voltage v lim v cut 0v v sensen to v ee int 429071 f02 t start , t cut v min v sensen to v ee int t dis t mps 429071 f03
ltc4290/ltc4271 11 429071f test timing diagrams figure 4. shut down delay timing figure 5. i 2 c interface timing v gaten v ee msd t msd 429071 f04 scl sda t 1 t 2 t 3 t r t f t 5 t 6 t 7 t 8 t 4 429071 f05
ltc4290/ltc4271 12 429071f i 2 c timing diagrams figure 6. writing to a register figure 7. reading from a register scl sda 429071 f06 ad6 01 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 ack ack start by master ack by slave ack by slave ack by slave frame 1 serial bus address byte frame 2 register address byte frame 3 data byte stop by master scl sda ad6 01 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack ack 01 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave ack by slave 429071 f07 stop by master repeated start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 register address byte frame 1 serial bus address byte frame 2 data byte ad6
ltc4290/ltc4271 13 429071f i 2 c timing diagrams figure 8. reading the interrupt register (short form) figure 9. reading from alert response address scl sda 429071 f08 ad6 1 0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 data byte stop by master scl sda 429071 f09 0 0 11 0 ad30 ad6 00 1 ad2 ad1 ad0 r/w ack ack1 start by master ack by slave no ack by master frame 1 alert response address byte frame 2 serial bus address byte stop by master
ltc4290/ltc4271 14 429071f pin functions ltc4290 v ee (pins 1, 30, 33, 40): main poe supply input. con - nect to a C45v to C57v supply, relative to agnd. voltage depends on pse type (type 1 or type 2). gaten (pins 2, 4, 7, 9, 22, 24, 27, 29): port n gate drive. gaten should be connected to the gate of the external mosfet for port n. when the mosfet is turned on, the gate voltage is driven to 12v (typ) above v ee . during a current limit condition, the voltage at gaten will be re - duced to maintain constant current through the external mosfet. if the fault timer expires, gaten is pulled down, turning the mosfet off and recording a port fault event. if the port is unused, float the gaten pin. outn (pins 3, 5, 8, 10, 21, 23, 26, 28): port n output voltage monitor. outn should be connected to the output port. a current limit foldback circuit limits the power dis - sipation in the external mosfet by reducing the current limit threshold when the drain-to-source voltage exceeds 10v. the port n power good bit is set when the voltage from outn to v ee drops below 2.4v (typ). a 500k resistor is connected internally from outn to agnd when the port is idle. if the port is unused, the outn pin must be floated. cap2 (pin 6): analog internal 4.3v power supply bypass capacitor. connect 0.1f ceramic cap to v ee . xio0 (pin 11): general purpose digital input output. logic signal between v ee and v ee + 4.3v. internal pull up. sensen (pins 12, 13, 14, 15, 16, 17, 18, 19): port n current sense input. sensen monitors the external mos - fet current via a 0.5 or 0.25 sense resistor between sensen and v ee . whenever the voltage across the sense resistor exceeds the overcurrent detection threshold v cut , the current limit fault timer counts up. if the voltage across the sense resistor reaches the current limit threshold v lim , the gaten pin voltage is lowered to maintain constant cur - rent in the external mosfet. see applications information for further details. if the port is unused, the sensen pin must be tied to v ee . xio1 (pin 20): general purpose digital input output. logic signal between v ee and v ee + 4.3v. internal pull up. agnd (pin 25): analog ground. connect agnd to the return for the v ee supply. dna (pin 36): data transceiver negative input output (analog). connect to dnd through a data transformer. dpa (pin 37): data transceiver positive input output (analog). connect to dpd through a data transformer. cna (pin 38): clock transceiver negative input output (analog). connect to cnd through a data transformer. cpa (pin 39): clock transceiver positive input output (analog). connect to cpd through a data transformer. vssk (exposed pad pin 41): kelvin sense to v ee . connect to sense resistor common node. do not connect directly to v ee plane. see layout guide. common pins nc, dnc (ltc4271 pins 7,13; ltc4290 pins 31, 32, 34, 35): all pins identified with nc or dnc must be left unconnected. ltc4271 ad0 (pin 1): address bit 0. tie the address pins high or low to set the starting i 2 c serial address to which the ltc4271 responds. the chip will respond to this address plus the next two incremental addresses. the base address of the first four ports will be (a 6 10a 3 a 2 a 1 a 0 )b. the second and third groups of four ports will respond at the next two logical addresses. internally pulled up to v dd . ad1 (pin 2): address bit 1. see ad0. ad2 (pin 3): address bit 2. see ad0. ad3 (pin 4): address bit 3. see ad0. ad6 (pin 5): address bit 6. see ad0. mid (pin 6): midspan mode input. when high, the ltc4271 acts as a midspan device. internally pulled down to dgnd. cpd (pin 8): clock transceiver positive input output (digital). connect to cpa through a data transformer.
ltc4290/ltc4271 15 429071f cnd (pin 9): clock transceiver negative input output (digital). connect to cna through a data transformer. dpd (pin 10): data transceiver positive input output (digital). connect to dpa through a data transformer. dnd (pin 11): data transceiver negative input output (digital). connect to dna through a data transformer. v dd33 (pins 12, 20): v dd io power supply. connect to a 3.3v power supply relative to dgnd. v dd33 must be bypassed to dgnd near the ltc4271 with at least a 0.1f capacitor. reset (pin 14): reset input, active low. when the reset pin is low, the ltc4290/ltc4271 is held inactive with all ports off and all internal registers reset to their power-up states. when reset is pulled high, the ltc4271 begins normal operation. reset can be connected to an exter - nal capacitor or rc network to provide a power turn-on delay. internal filtering of the reset pin prevents glitches less than 1s wide from resetting the ltc4290/ltc4271. internally pulled up to v dd . int (pin 15): interrupt output, open drain. int will pull low when any one of several events occur in the ltc4271. it will return to a high impedance state when bits 6 or 7 are set in the reset pb register (1ah). the int signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. individual int events can be disabled using the int mask register (01h). see ltc4271 software programming documentation for more information. the int pin is only updated between i 2 c transactions. sdaout (pin 16): serial data output, open drain data output for the i 2 c serial interface bus. the ltc4271 uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a stan - dard bidirectional sda pin, tie sdaout and sdain together. see applications information for more information. sdain (pin 17): serial data input. high impedance data input for the i 2 c serial interface bus. the ltc4271 uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. see applications information for more information. scl (pin 18): serial clock input. high impedance clock input for the i 2 c serial interface bus. the scl pin should be connected directly to the i 2 c scl bus line. scl must be tied high if the i 2 c serial interface bus is not used. cap1 (pin 19): core power supply bypass capacitor. con - nect a 1f bypass capacitance to dgnd for the internal 1.8v regulator. do not use other capacitor values. auto (pin 21): auto pin mode input. auto pin mode allows the ltc4271 to detect and power up a pd even if there is no host controller present on the i 2 c bus. the auto pin determines the state of the internal registers when the ltc4271 is reset or comes out of v dd uvlo (see ltc4271 software programming documentation). the states of these register bits can subsequently be changed via the i 2 c interface. internally pulled down to dgnd. must be tied locally to either v dd or dgnd. gp1 (pin 22): general purpose digital input output for customer applications. referenced to dgnd. gp0 (pin 23): general purpose digital input output for customer applications. referenced to dgnd. msd (pin 24): maskable shutdown input. active low. when pulled low, all ports that have their corresponding mask bit set in the mconfig register (17h) will be reset. internal filtering of the msd pin prevents glitches less than 1s wide from resetting ports. the msd pin mode register can configure the msd pin polarity. internally pulled up to v dd . dgnd (exposed pad pin 25): digital ground. dgnd should be connected to the return from the v dd supply. pin functions
ltc4290/ltc4271 16 429071f overview power over ethernet, or poe, is a standard protocol for sending dc power over copper ethernet data wiring. the ieee group that administers the 802.3 ethernet data stan - dards added poe powering capability in 2003. this original poe spec, known as 802.3af, allowed for 48v dc power at up to 13w. this initial specification was widely popular, but 13w was not adequate for some requirements. in 2009, the ieee released a new standard, known as 802.3at or poe + , increasing the voltage and current requirements to provide 25w of power. the ieee standard also defines poe terminology. a device that provides power to the network is known as a pse, or power sourcing equipment, while a device that draws power from the network is known as a pd, or powered device. pses come in two types: endpoints (typically network switches or routers), which provide data and power; and midspans, which provide power but pass through data. midspans are typically used to add poe capability to existing non-poe networks. pds are typically ip phones, wireless access points, security cameras, and similar devices. applications information ltc4290/ltc4271 product overview the ltc4290/ltc4271 is a fourth generation 8-port pse controller that implements eight pse ports in either an endpoint or midspan design. virtually all necessary circuitry is included to implement an ieee 802.3at compliant pse design, requiring only an external power mosfet and sense resistor per channel; these minimize power loss compared to alternative designs with onboard mosfets and increase system reliability in the event a single channel fails. the ltc4290/ltc4271 offers advanced fourth generation pse features, including per-port current monitoring, v ee monitoring, port current policing, one second current averaging and four general purpose input/output pins. the ltc4290/ltc4271 chipset implements a proprietary isolation scheme for inter-chip communication. this architecture dramatically reduces bom cost by replacing expensive opto-isolators and isolated power supplies with a single low-cost transformer. ltc4290/ltc4271 is a fully ieee-compliant type 2 pse supporting autonomous detection, classification and powering of type 1 and type 2 pds. figure 10. power over ethernet system diagram 429071 f10 s1b s1b smaj58a 0.22f 100v x7r 1 f 100v x7r tx rx rx tx smaj58a 58v data pair data pair v ee sense gate out v dd33 int scl sdain sdaout 0.25 spare pair spare pair 1/8 ltc4290/ ltc4271 dgnd agnd i 2 c 3.3v interrupt ?48v cat 5 20 max roundtrip 0.05f max rj45 4 5 4 5 1 2 1 2 3 6 3 6 7 8 7 8 rj45 1n4002 4 1n4002 4 pse pd r class ?48v in pwrgd ?48v out ltc4265 gnd dc/dc converter 5f c in 300f + ? v out gnd 0.1 f
ltc4290/ltc4271 17 429071f poe basics common ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as cat-5 cable), transformer-coupled at each end to avoid ground loops. poe systems take advantage of this coupling ar - rangement by applying voltage between the center-taps of the data transformers to transmit power from the pse to the pd without affecting data transmission. figure 10 shows a high level poe system schematic. to avoid damaging legacy data equipment that does not expect to see dc voltage, the poe spec defines a protocol that determines when the pse may apply and remove power. valid pds are required to have a specific 25k com - mon mode resistance at their input. when such a pd is connected to the cable, the pse detects this signature resistance and turns on the power. when the pd is later disconnected, the pse senses the open circuit and turns power off. the pse also turns off power in the event of a current fault or short circuit. when a pd is detected, the pse optionally looks for a classification signature that tells the pse the maximum power the pd will draw. the pse can use this information to allocate power among several ports, to police the current consumption of the pd, or to reject a pd that will draw more power than the pse has available. the classification step is optional; if a pse chooses not to classify a pd, it must assume that the pd is a 13w (full 802.3af power) device. new in 802.3at the newer 802.3at standard supersedes 802.3af and brings several new features: ? a pd may draw as much as 25.5w. such pds (and the pses that support them) are known as type 2. older 13w 802.3af equipment is classified as type 1. type 1 pds will work with all pses; type 2 pds may require type 2 pses to work properly. the ltc4290/ltc4271 applications information is designed to work in both type 1 and type 2 pse de - signs, and also supports non-standard configurations at higher power levels. ? the classification protocol is expanded to allow type 2 pses to detect type 2 pds, and to allow type 2 pds to determine if they are connected to a type 2 pse. two versions of the new classification protocol are avail - able: an expanded version of the 802.3af class pulse protocol, and an alternate method integrated with the existing lldp protocol (using the ethernet data path). the ltc4290/ltc4271 fully supports the new class pulse protocol and is also compatible with the lldp protocol (which is implemented in the data communica - tions layer, not in the poe circuitry). ? fault protection current levels and timing are adjusted to reduce peak power in the mosfet during a fault; this allows the new 25.5w power levels to be reached using the same mosfets as older 13w designs. backward compatibility the ltc4290/ltc4271 chipset is designed to be backward compatible with the LTC4266, operating in type 2 mode, without software changes; only minor layout changes are required to implement a fully compliant ieee 802.3at design. some LTC4266 registers have been obsoleted in the ltc4290/ltc4271 chipset. the obsoleted registers are not required for 802.3at compliant pse operation. for more details about software differences between the LTC4266 and ltc4290/ltc4271, refer to the ltc4271 software programming document. operation with high power mode disabled is obsoleted in the ltc4290/ltc4271 chipset. all operations previously available in low power mode are fully implemented as a subset of the high power mode capabilities.
ltc4290/ltc4271 18 429071f operating modes the ltc4290/ltc4271 includes eight independent ports, each of which can operate in one of four modes: manual, semi-auto, auto pin, or shutdown. table 1. operating modes mode auto pin opmd detect/ class power-up automatic i cut /i lim assignment auto pin 1 11b enabled at reset automatically yes reserved 0 11b n/a n/a n/a semi-auto 0 10b host enabled upon request no manual 0 01b once upon request upon request no shutdown 0 00b disabled disabled no in manual mode, the port waits for instructions from the host system before taking any action. it runs a single detection or classification cycle when commanded to by the host, and reports the result in its port status register. the host system can command the port to turn on or off the power at any time. in semi-auto mode, the port repeatedly attempts to detect and classify any pd attached to it. it reports the status of these attempts back to the host, and waits for a command from the host before turning on power to the port. the host must enable detection (and optionally classification) for the port before detection will start. auto pin mode operates the same as semi-auto mode except it will automatically turn on the power to the port if detection is successful. auto pin mode will autonomously set the i cut and i lim values based on the class result. this operational mode is only valid if the auto pin is high at reset or power-up and remains high during operation. in shutdown mode, the port is disabled and will not detect or power a pd. applications information regardless of which mode it is in, the ltc4290/ltc4271 will remove power automatically from any port that gener - ates a current limit fault. it will also automatically remove power from any port that generates a disconnect event if disconnect detection is enabled. the host controller may also command the port to remove power at any time. reset and the auto/mid pins the initial ltc4290/ltc4271 configuration depends on the state of the auto and mid pins during reset. reset occurs at power-up, or whenever the reset pin is pulled low or the global reset all bit is set. changing the state of auto or mid after power-up will not properly change the port behavior of the ltc4290/ltc4271 until a reset occurs. although typically used with a host controller, the ltc4290/ ltc4271 can also be used in a standalone mode with no connection to the serial interface. if there is no host pres - ent, the auto pin must be tied high so that, at reset, all ports will be configured to operate automatically. each port will detect and classify repeatedly until a pd is discovered, set i cut and i lim according to the classification results, apply power to valid pds, and remove power when a pd is disconnected. table 2 shows the i cut and i lim values that will be auto - matically set in standalone (auto pin) mode, based on the discovered class. table 2. i cut and i lim values in standalone mode class i cut i lim class 1 112ma 425ma class 2 206ma 425ma class 3 or 0 375ma 425ma class 4 638ma 850ma the automatic setting of i cut and i lim values only occurs if the ltc4290/ltc4271 is reset with the auto pin high. if the standalone application is a midspan, the mid pin must be tied high to enable correct midspan detection timing.
ltc4290/ltc4271 19 429071f detection detection overview to avoid damaging network devices that were not designed to tolerate dc voltage, a pse must determine whether the connected device is a real pd before applying power. the ieee specification requires that a valid pd have a common- mode resistance of 25k 5% at any port voltage below 10v. the pse must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k or below 15k (shaded regions in figure 11). the pse may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. in particular, the pse must reject standard computer network ports, many of which have 150 common-mode termination resistors that will be damaged if power is applied to them (the black region at the left of figure 11). applications information figure 11. ieee 802.3af signature resistance ranges ing currents are measured and subtracted. both methods must report valid resistances for the port to report a valid detection. pd signature resistances between 17k and 29k (typically) are detected as valid and reported as detect good in the corresponding port status register. values outside this range, including open and short circuits, are also reported. if the port measures less than 1v at the first forced-current test, the detection cycle will abort and short circuit will be reported. table 3 shows the possible detection results. table 3. detection status measured pd signature detection result incomplete or not yet tested detect status unknown < 2.4k short circuit capacitance > 2.7f c pd too high 2.4k < r pd < 17k r sig too low 17k < r pd < 29k detect good > 29k r sig too high > 50k open circuit voltage > 10v port voltage outside detect range resistance pd pse 0 10k 15k 429071 f11 19k 26.5k 26.25k 23.75k 150 (nic) 20k 30k 33k 4-point detection the ltc4290/ltc4271 uses a 4-point detection method to discover pds. false-positive detections are minimized by checking for signature resistance with both forced-current and forced-voltage measurements. initially, two test currents are forced onto the port (via the outn pin) and the resulting voltages are measured. the detection circuitry subtracts the two v-i points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see figure 12). if the forced- current detection yields a valid signature resistance, two test voltages are then forced onto the port and the result - figure 12. pd detection first detection point second detection point valid pd 25k slope 275 165 current (a) 0v-2v offset voltage 429071 f12
ltc4290/ltc4271 20 429071f applications information more on operating modes the ports operating mode determines when the ltc4290/ ltc4271 runs a detection cycle. in manual mode, the port will idle until the host orders a detect cycle. it will then run detection, report the results, and return to idle to wait for another command. in semi-auto mode, the ltc4290/ltc4271 autonomously polls a port for pds, but it will not apply power until com - manded to do so by the host. the port status register is updated at the end of each detection cycle. if a valid signature resistance is detected and classification is enabled, the port will classify the pd and report that result as well. the port will then wait for at least 100ms (or 2 seconds if midspan mode is enabled), and will repeat the detection cycle to ensure that the data in the port status register is up-to-date. if the port is in semi-auto mode and high power opera - tion is enabled, the port will not turn on in response to a power-on command unless the current detect result is detect good. any other detect result will generate a t start fault if a power-on command is received. in high power mode the port must be placed in manual mode to force a port on regardless of detect outcome. behavior in auto pin mode is similar to semi-auto; however, after detect good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. in standalone (auto pin) mode, the i cut and i lim thresholds are automatically set; see the reset and the auto/mid pins section for more information. the signature detection circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding detect enable bit is cleared. detection of legacy pds proprietary pds that predate the original ieee 802.3af stan - dard are commonly referred to today as legacy devices. one type of legacy pd uses a large common mode capacitance (>10f) as the detection signature. note that pds in this range of capacitance are defined as invalid, so a pse that detects legacy pds is technically noncompliant with the ieee spec. the ltc4290/ltc4271 can be configured to detect this type of legacy pd. legacy detection is disabled by default, but can be manually enabled on a per-port basis. when enabled, the port will report detect good when it sees either a valid ieee pd or a high-capacitance legacy pd. with legacy mode disabled, only valid ieee pds will be recognized. classification 802.3af classification a pd may optionally present a classification signature to the pse to indicate the maximum power it will draw while operating. the ieee specification defines this signature as a constant current draw when the pse port voltage is in the v class range (between 15.5v and 20.5v), with the current level indicating one of 5 possible pd classes. figure 13 shows a typical pd load line, starting with the slope of the 25k signature resistor below 10v, then transitioning to the classification signature current (in this case, class 3) in the v class range. table 4 shows the possible clas - sification values. table 4. 802.3af and 802.3at classification values class result class 0 no class signature present; treat like class 3 class 1 3w class 2 7w class 3 13w class 4 25.5w (type 2)
ltc4290/ltc4271 21 429071f applications information if classification is enabled, the port will classify the pd immediately after a successful detection cycle in semi-auto or auto pin modes, or when commanded to in manual mode. it measures the pd classification signature by ap - plying 18v for 12ms (both values typical) to the port via the outn pin and measuring the resulting current; it then reports the discovered class in the port status register. if the ltc4290/ltc4271 is in auto pin mode, it will ad - ditionally use the classification result to set the i cut and i lim thresholds. see the reset and the auto/mid pin section for more information. the classification circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding class enable bit is cleared. figure 13. pd classification path. lldp classification requires the pse to power the pd as a standard 802.3af (type 1) device. it then waits for the host to perform lldp communication with the pd and update the pse port data. the ltc4290/ltc4271 supports changing the i lim and i cut levels on the fly, allowing the host to complete lldp classification. the second 802.3at classification method, known as 2-event classification or ping-pong, is supported by the ltc4290/ltc4271. a type 2 pd that is requesting more than 13w will indicate class 4 during normal 802.3af classification. if the ltc4290/ltc4271 sees class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9v), pauses briefly, and then re-runs classification to verify the class 4 reading (figure 1). it also sets a bit in the high power status register to indicate that it ran the second classification cycle. the second cycle alerts the pd that it is connected to a type 2 pse which can supply type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the ports high power mode register. note that a ping- pong enabled port only runs the second classification cycle when it detects a class 4 device; if the first cycle returns class 0 to 3, the port determines it is connected to a type 1 pd and does not run the second classification cycle. invalid type 2 class combinations the 802.3at specification defines a type 2 pd class signa - ture as two consecutive class 4 results; a class 4 followed by a class 0-3 is not a valid signature. in auto pin mode, the ltc4290/ltc4271 will power a detected pd regardless of the classification results, with one exception: if the pd presents an invalid type 2 signature (class 4 followed by class 0 to 3), the ltc4290/ltc4271 will not provide power and will restart the detection process. to aid in diagnosis, the port status register will always report the results of the last class pulse, so an invalid class 4Cclass 2 combination would report a second class pulse was run in the high power status register (which implies that the first cycle found class 4), and class 2 in the port status register. voltage (v class ) 0 current (ma) 60 50 40 30 20 10 0 5 10 15 20 429071 f13 25 typical class 3 pd load line 48ma 33ma pse load line 23ma 14.5ma 6.5ma class 4 class 2 class 1 class 0 class 3 over current 802.3at 2-event classification the 802.3at specification defines two methods of classify- ing a type 2 pd. ltc4290/ltc4271 parts support 802.3at 2-event classification. one method adds extra fields to the ethernet lldp data protocol; although the ltc4290/ltc4271 is compatible with this classification method, it cannot perform clas - sification directly since it doesnt have access to the data
ltc4290/ltc4271 22 429071f power control the primary function of the ltc4290/ltc4271 is to con - trol the delivery of power to the pse port. it does this by controlling the gate drive voltage of an external power mosfet while monitoring the current via an external sense resistor and the output voltage at the out pin. this circuitry serves to couple the raw v ee input supply to the port in a controlled manner that satisfies the pds power needs while minimizing both power dissipation in the mosfet and disturbances on the v ee backplane. inrush control once the command has been given to turn on a port, the ltc4290/ltc4271 ramps up the gate pin of that ports external mosfet in a controlled manner. under normal power-up circumstances, the mosfet gate will rise until the port current reaches the inrush current limit level (typically 425ma), at which point the gate pin will be servoed to maintain the specified i inrush current. during this inrush period, a timer (t start ) runs. when output charging is complete, the port current will fall and the gate pin will be allowed to continue rising to fully enhance the mosfet and minimize its on-resistance. the final v gs is nominally 12v. the inrush period is maintained until the t start timer expires. at this time if the inrush current limit level is still exceeded, the port will be turned back off and a t start fault reported. current limit each ltc4290/ltc4271 port includes two current limiting thresholds (i cut and i lim ), each with a corresponding timer (t cut and t lim ). setting the i cut and i lim thresholds depends on several factors: the class of the pd, the volt - age of the main supply (v ee ), the type of pse (type 1 or type 2), the sense resistor (0.5 or 0.25), the soa of the mosfet, and whether or not the system is required to enforce class current levels. applications information per the ieee specification, the ltc4290/ltc4271 will al - low the port current to exceed i cut for a limited period of time before removing power from the port, whereas it will actively control the mosfet gate drive to keep the port current below i lim . the port does not take any action to limit the current when only the i cut threshold is exceeded, but does start the t cut timer. if the current drops below the i cut current threshold before its timer expires, the t cut timer counts back down, but at 1/16 the rate that it counts up. if the t cut timer reaches 60ms (typical) the port is turned off and the port t cut fault is set. this allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. the i lim current limiting circuit is always enabled and ac - tively limiting port current. the t lim timer is enabled only when the t lim enable bit is set. this allows t lim to be set to a shorter value than t cut to provide more aggressive mosfet protection and turn off a port before mosfet damage can occur. the t lim timer starts when the i lim threshold is exceeded. when the t lim timer reaches 12ms (typical) the port is turned off and the port t lim fault is set. when the t lim enable bit is disabled t lim behaviors are tracked by the t cut timer, which counts up during both i lim and i cut events. i cut is typically set to a lower value than i lim to allow the port to tolerate minor faults without current limiting. per the ieee specification, the ltc4290/ltc4271 will au - tomatically set i lim to 425ma (shown in bold in table 5) during inrush at port turn-on, and then switch to the programmed i lim setting once inrush has completed. to maintain ieee compliance, i lim should be kept at 425ma for all type 1 pds, and 850ma if a type 2 pd is detected. i lim is automatically reset to 425ma when a port turns off.
ltc4290/ltc4271 23 429071f applications information table 5. example current limit settings i lim (ma) internal register setting (hex) r sense = 0.5 r sense = 0.25 53 88 106 08 88 159 89 213 80 08 266 8a 319 09 89 372 8b 425 00 80 478 8e 531 92 8a 584 cb 638 10 90 744 d2 9a 850 40 c0 956 4a ca 1063 50 d0 1169 5a da 1275 60 e0 1488 52 49 1700 40 1913 4a 2125 50 2338 5a 2550 60 2975 52 i lim foldback the ltc4290/ltc4271 features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. this keeps mosfet power dissipation at safe levels for typical 802.3af mosfets, even at extended 802.3at power levels. current limit and foldback behavior are programmable on a per-port basis. table 5 gives examples of recommended i lim register settings. the ltc4290/ltc4271 will support current levels well beyond the maximum values in the 802.3at specification. the shaded areas in table 5 indicate settings that may require a larger external mosfet, additional heat sinking, or setting t lim enable. mosfet fault detection ltc4290/ltc4271 pse ports are designed to tolerate significant levels of abuse, but in extreme cases it is pos - sible for the external mosfet to be damaged. a failed mosfet may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the ltc4290 sense pin to rise to an abnormally high voltage. a failed mosfet may also short from gate to drain, causing the ltc4290 gate pin to rise to an abnormally high voltage. the ltc4290 out, sense and gate pins are designed to tolerate up to 80v faults without damage. if the ltc4290/ltc4271 sees any of these conditions for more than 180s, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a fet bad fault. this is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. if the mosfet is in fact bad, the fault will quickly return, and the port will disable itself again. the remaining ports of the ltc4290/ltc4271 are unaffected. an open or missing mosfet will not trigger a fet bad fault, but will cause a t start fault if the ltc4290/ltc4271 attempts to turn on the port. port current readback the ltc4290/ltc4271 measures the current at each port with an internal a/d converter. port data is only valid when the port power is on and reads zero at all other times. the converter has two modes: ? 100ms mode: samples are taken continuously and the measured value is updated every 100ms ? 1s mode: samples are taken continuously; a moving 1 second average is updated every 100ms
ltc4290/ltc4271 24 429071f port current policing the ltc4290/ltc4271 can augment t cut current monitor - ing with a policing function to track the one second current averages. a port violating the user-specified port police threshold will be shut off with both a t cut and police event recorded. a port current police event can be differentiated from a port t cut violation by reading both events bits; both bits are set for a police violation while only the t cut bit is set for t cut timer violations. port voltage readback the ltc4290/ltc4271 measures the output voltage at each port with an internal a/d converter. port data is only valid when the port power is on and reads zero at all other times. disconnect the ltc4290/ltc4271 monitors powered ports to ensure the pd continues to draw the minimum specified current. a disconnect timer counts up whenever port current is below 7.5ma (typ), indicating that the pd has been disconnected. if the t dis timer expires, the port will be turned off and the disconnect bit in the fault event register will be set. if the current returns before the t dis timer runs out, the timer resets. as long as the pd exceeds the minimum current level more often than t dis , it will remain powered. although not recommended, the dc disconnect feature can be disabled by clearing the corresponding enable bits. note that this defeats the protection mechanisms built into the ieee specification, since a powered port will stay powered after the pd is removed. if the still-powered port is subsequently connected to a non-poe data device, the device may be damaged. the ltc4290/ltc4271 does not include ac disconnect circuitry, but includes ac disconnect enable bits to main - tain compatibility with the ltc4259a. if the ac disconnect enable bits are set, dc disconnect will be used. applications information masked shutdown the ltc4290/ltc4271 provides a low latency port shed - ding feature to quickly reduce the system load when required. by allowing a pre-determined set of ports to be turned off, the current on an overloaded main power supply can be reduced rapidly while keeping high priority devices powered. each port can be configured to high or low priority; all low-priority ports will shut down within 6.5s after the msd pin is pulled low, high priority ports will remain powered. if a port is turned off via msd, the corresponding detection and classification enable bits are cleared, so the port will remain off until the host explicitly re-enables detection. in the ltc4290/ltc4271 chipset the active level of msd is register configurable as active high or low. the default is LTC4266-compatible active low behavior. v ee readback the ltc4290/ltc4271 measures the v ee voltage with an internal 12-bit a/d converter. general purpose io two sets of general purpose io pins are available in the ltc4290/ltc4271 chipset. the first set of general purpose io are gp1 and gp0. these fully bidirectional io are 3.3v cmos io on the ltc4271 chip. the second set of general purpose io pins are xio1 and xio0. these fully bidirectional io are 4.3v cmos io on the ltc4290 chip. code download ltc4271 firmware is field-upgradable by downloading and executing ram images. ram images are volatile and must be re-downloaded after each v dd power cycle, but will remain valid during reset and v ee power events. contact linear technology for code download procedures and ram images.
ltc4290/ltc4271 25 429071f applications information serial digital interface overview the ltc4290/ltc4271 communicates with the host us - ing a standard smbus/i 2 c 2-wire interface. the ltc4290/ ltc4271 is a slave-only device, and communicates with the host master using the standard smbus protocols. interrupts are signaled to the host via the int pin. the timing diagrams (figures 5 through 9) show typical communication waveforms and their timing relationships. more information about the smbus data protocols can be found at www.smbus.org. the ltc4290/ltc4271 requires both the v dd and v ee sup- ply rails to be present for the serial interface to function. bus addressing the ltc4290/ltc4271s primary 7-bit serial bus address is a 6 10a 3 a 2 a 1 a 0 b, with bit 6 controlled by ad6 and the lower four bits set by the ad3-ad0 pins; this allows up to 16 ltc4290/ltc4271s, on a single bus. sixteen ltc4290/ ltc4271 are equivalent to 32 quad pses or 128 ports. all ltc4290/ltc4271s also respond to the broadcast address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple ltc4290/ ltc4271s in a single transaction. if the ltc4290/ltc4271 is asserting the int pin, it will also respond to the alert response address (0001100b) per the smbus specification. each ltc4290/ltc4271 is logically composed of two quads of four ports each. each quad occupies separate, contigu - ous i 2 c addresses. the ad6, ad3-0 pins set the address of the base quad while the second quad is consecutively numbered. i 2 c addresses outside of the x10xxxxb range are considered illegal and will not respond. each internal quad is independent of the other quad, with the exception of writes to the chip reset, msd inversion and general purpose input output registers. these registers are global in nature and will affect all quads. figure 14. example i 2 c bus addressing interrupts and smbalert most ltc4290/ltc4271 port events can be configured to trigger an interrupt, asserting the int pin and alerting the host to the event. this removes the need for the host to poll the ltc4290/ltc4271, minimizing serial bus traf - fic and conserving host cpu cycles. multiple ltc4290/ ltc4271s can share a common int line, with the host using the smbalert protocol (ara) to determine which ltc4290/ltc4271 caused an interrupt. register description for information on serial bus usage and device configura- tion and status, refer to the ltc4271 software program - ming documentation. isolation requirements ieee 802.3 ethernet specifications require that network segments (including poe circuitry) be electrically isolated from the chassis ground of each network interface device. however, network segments are not required to be isolated from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system. quad 0 quad 1 ltc4271 ad0 ad1 ad2 ad3 ad6 scl sdain sdaout scl sda ad0 3.3v ad1 ad2 ad3 ad6 scl sdain sdaout i 2 c address 0100000 0100001 quad 0 quad 1 ltc4271 i 2 c address 0100111 0101000 429071 f14
ltc4290/ltc4271 26 429071f applications information for simple devices such as small poe switches, the isola - tion requirement can be met by using an isolated main power supply for the entire device. this strategy can be used if the device has no electrically conducting ports other than twisted-pair ethernet. in this case, the sdain and sdaout pins can be tied together and will act as a standard i 2 c/smbus sda pin. if the device is part of a larger system, contains additional external non-ethernet ports, or must be referenced to protective ground for some other reason, the power over ethernet subsystem must be electrically isolated from the rest of the system. the ltc4290/ltc4271 chipset simplifies pse isolation by allowing the ltc4271 chip to reside on the non-isolated side. there it can receive power from the main logic sup - ply and connect directly to the i 2 c/smbus bus. isolation between the ltc4271 and ltc4290 is implemented using a proprietary transformer-based communication protocol. additional details are provided in the serial bus isolation section of this data sheet. external component selection power supplies and bypassing the ltc4290/ltc4271 requires two supply voltages to operate. v dd requires 3.3v (nominally) relative to dgnd. v ee requires a negative voltage of between C45v and C57v for type 1 pses or C51v to C57v for type 2 pses, relative to agnd. digital power supply v dd provides digital power for the ltc4271 processor, and draws a maximum of 15ma. a ceramic decoupling cap of at least 0.1f should be placed from v dd to dgnd, as close as practical to each ltc4271 chip. a 1.8v core voltage supply is generated internally and requires a 1f ceramic decoupling cap between the cap1 pin and dgnd. in the ltc4290/ltc4271, v dd should be delivered by the host controllers non-isolated 3.3v supply. to maintain required isolation agnd and dgnd must not be con - nected in any way. main poe power supply v ee is the main isolated poe supply that provides power to the pds. because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. for minimum ir loss and best system efficiency, set v ee near maximum amplitude (57v), leaving enough margin to account for transient over or undershoot, temperature drift, and the line regulation specifications of the particular power supply used. bypass capacitance between agnd and v ee is very im - portant for reliable operation. if a short circuit occurs at one of the output ports it can take as long as 1s for the ltc4290 to begin regulating the current. during this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a voltage transient on the v ee supply and possibly causing the ltc4290/ltc4271 to reset due to a uvlo fault. a 1f, 100v x7r capacitor placed near the v ee pin along with an electrolytic bulk capacitor of at least 47f is recommended to minimize spurious resets. serial bus isolation the ltc4290/ltc4271 chipset uses transformers to isolate the ltc4271 from the ltc4290. in this case, the sdain and sdaout pins can be shorted to each other and tied directly to the i 2 c/smbus bus. the transformers should be 10base-t or 10/100base-t with a 1:1 turns ratio. it is important that the selected transformers do not have common-mode chokes. these transformers typically provide 1500v of isolation between the ltc4271 and the ltc4290. for proper operation strict layout guidelines must be met.
ltc4290/ltc4271 27 429071f applications information external mosfet careful selection of the power mosfet is critical to system reliability. ltc recommends either fairchild irfm120a, fdt3612, fdmc3612 or philips pht6nq10t for their proven reliability in type 1 and type 2 pse applications. soa curves are not a reliable specification for mosfet selection. contact ltc applications before using a mosfet other than one of these recommended parts. sense resistor the ltc4290/ltc4271 is designed to use 0.25 current sense resistors to reduce power dissipation. four com- monly available 1 resistors (sized according to power dissipation) can be used in parallel in place of a single figure 15. ltc4290/ltc4271 proprietary isolation 0.25 resistor. in order to meet the i cut and i lim accuracy required by the ieee specification, the sense resistors should have 1% tolerance or better, and no more than 200ppm/c temperature coefficient. in addition, the sense resistors must meet strict layout guidelines. port output cap each port requires a 0.22f cap across its outputs to keep the ltc4290 stable while in current limit during startup or overload. common ceramic capacitors often have signifi - cant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. to minimize this problem, x7r ceramic capacitors rated for at least 100v are recommended and must be located close to the pse. ?? 3.3v 3.3v 0.1f ?54v 100 100 100 100 t1 ?? 3.3v 1f 1f 0.1f ?54v 100 100 100 100 t2 gp0 gp1 mid reset msd int auto scl ad0 ad1 ad2 ad3 ad6 dgnd cap1 cap2 dnd dpd cnd cpd dna sense1 gate1 out1 ltc4290 dpa cna cpa xio0 xio1 0.22f 100v 0.22f 100v s1b s1b ?54v ?54v 429071 f15 ?54v ?54v s1b s1b portn port1 sdain sdaout ltc4271 no isolation required on i 2 c interface v dd33 2nf, 2kv v ee sensen gaten outn agnd vssk 0.25 0.25 >47f system bulk cap +
ltc4290/ltc4271 28 429071f applications information figure 16. ltc4290 discharge protection esd/cable discharge protection ethernet ports can be subject to significant esd events when long data cables, each potentially charged to thou - sands of volts, are plugged into the low impedance of the rj45 jack. to protect against damage, each port requires a pair of clamp diodes; one to agnd and one to v ee (figure 16). an additional surge suppressor is required for each ltc4290 chip from v ee to agnd. the diodes at the ports steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the v ee bypass capacitance. the surge suppressor has the additional benefit of protecting the ltc4290 from transients on the v ee supply. s1b diodes work well as port clamp diodes, and an smaj58a or equivalent is recommended for the v ee surge suppressor. layout guidelines strict adherence to board layout, parts placement and routing guidelines is critical for optimal current read - ing accuracy, ieee compliance, system robustness, and thermal dissipation. refer to the dc1842a demo board as a layout reference. contact ltc applications to obtain a full set of layout guidelines, example layouts and boms. 0.22f 0.25 s1b portn outn gaten sensen a gnd v ee s1b 429071 f16 ?54v smaj58a ltc4290 0.1f
ltc4290/ltc4271 29 429071f typical application 0.01f 200v 0.01f 200v 1 2 3 4 5 6 7 8 rj45 connector ?? 3.3v ?54v 100 100 t2 t3 ?? 3.3v ?54v ?54v isolated isolated gnd ?54v 100 100 gp0 gp1 mid reset msd int auto scl ad0 ad1 ad2 ad3 ad6 dgnd v ee vssk cap1 cap2 dnd dpd cnd cpd dna agnd dpa cna cpa out8 out1 gate1 sense1 gate8 sense8 xio0 xio1 429071 ta02 sdain sdaout ltc4271 ltc4290 v dd33 1f 3.3v 0.1f 1f 1f 2nf 2000v smaj58a 1f 100v x7r 0.1f + >47f system bulk cap s1b 1 7 8 2 t1 0.25, 1% rs 0.22f 100v x7r s1b fdmc3612 ? ? ?? ? ? ? ? ?? ? ? 0.01f 200v 0.01f 200v 0.01f 200v 0.01f 200v 7575 7575 1 2 3 4 5 6 7 8 rj45 connector phy (network physical layer chip) complete 8-port pse
ltc4290/ltc4271 30 429071f 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present pin 1 top mark (note 6) 0.40 0.10 2423 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 x 45o chamfer 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc4290/ltc4271 31 429071f uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 x 45o chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc4290/ltc4271 32 429071f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0812 ? printed in usa related parts part number description comments ltc4257-1 ieee 802.3af pd interface controller internal 100v, 400ma switch, dual current limit, programmable class ltc4263 single ieee 802.3af pse controller internal fet switch ltc4263-1 high power single poe pse controller with internal fet switch ltc4265 ieee 802.3at pd interface controller internal 100v, 1a switch, 2-event classification recognition LTC4266 quad ieee 802.3at poe pse controller with programmable i cut /i lim , 2-event classification, and port current and voltage monitoring ltc4267 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, dual inrush current, programmable class ltc4267-1 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, programmable class, 200khz constant frequency pwm ltc4267-3 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, programmable class, 300khz constant frequency pwm ltc4269-1 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable class, synchronous no-opto flyback controller, 50khz to 250khz, aux support ltc4269-2 ieee 802.3af pd interface with integrated forward switching regulator 2-event classification, programmable class, synchronous forward controller, 100khz to 500khz, aux support ltc4270/ ltc4271 12-port poe/poe + /ltpoe ++? pse controller transformer isolation, supports type 1, type 2 and ltpoe ++ pds ltc4274 single ieee 802.3at poe pse controller with programmable i cut /i lim , 2-event classification, and port current and voltage monitoring ltc4278 ieee 802.3af pd interface with integrated flyback switching regulator 2-event classification, programmable class, synchronous no-opto flyback controller, 50khz to 250khz, 12v aux support ltc4311 smbus/ i 2 c accelerator improved i 2 c rise time, ensures data integrity typical application 0.01f 200v 0.01f 200v 1 2 3 4 5 6 7 8 rj45 connector ?? 3.3v ?54v 100 100 t2 t3 ?? 3.3v ?54v ?54v isolated isolated gnd ?54v 100 100 gp0 gp1 mid reset msd int auto scl ad0 ad1 ad2 ad3 ad6 dgnd v ee vssk cap1 cap2 dnd dpd cnd cpd dna agnd dpa cna cpa out8 out1 gate1 sense1 gate8 sense8 xio0 xio1 429071 ta03 sdain sdaout ltc4271 ltc4290 v dd33 1f 3.3v 0.1f 1f 1f 2nf 2000v smaj58a 1f 100v x7r 0.1f + >47f system bulk cap s1b 1 7 8 2 t1 0.25, 1% rs 0.22f 100v x7r s1b fdmc3612 ? ? ?? ? ? ? ? ?? ? ? 0.01f 200v 0.01f 200v 0.01f 200v 0.01f 200v 7575 7575 1 2 3 4 5 6 7 8 rj45 connector phy (network physical layer chip) complete 8-port pse

▲Up To Search▲

Price & Availability of LTC4266

	To Download LTC4266 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .